SCHEDULE: NOV 16-21, 2014

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ENTIRE WEEK SUNDAY MONDAY TUESDAY WEDNESDAY THURSDAY FRIDAY

Scaling the Power Wall: A Path to Exascale

SESSION: Power and Energy Efficiency

EVENT TYPE: Papers

TIME: 11:30AM - 12:00PM

SESSION CHAIR: Kirk Cameron

AUTHOR(S):Oreste Villa, Daniel R. Johnson, Mike O'Connor, Evgeny Bolotin, David W. Nellans, Justin Luitjens, Nikolai Sakharnykh, Peng Wang, Paulius Micikevicius, Anthony Scudiero, Stephen W. Keckler, William J. Dally

ROOM:393-94-95

ABSTRACT:

Modern scientific discovery is driven by an insatiable demand for computing performance. The HPC community is targeting development of supercomputers able to sustain 1 ExaFlops by the year 2020 and power consumption is the primary obstacle to achieving this goal. A combination of architectural improvements, circuit design, and manufacturing technologies must provide over a 20x improvement in energy efficiency. In this paper, we present some of the progress NVIDIA Research is making toward the design of Exascale systems by tailoring features to address the scaling challenges of performance and energy efficiency. We evaluate several architectural concepts for a set of HPC applications demonstrating expected energy efficiency improvements resulting from circuit and packaging innovations such as low-voltage SRAM, low-energy signaling, and on-package memory. Finally, we discuss the scaling of these features with respect to future process technologies and provide power and performance projections for our Exascale research architecture.

Chair/Author Details:

Kirk Cameron (Chair) - Virginia Polytechnic Institute and State University

Oreste Villa - NVIDIA Corporation

Daniel R. Johnson - NVIDIA Corporation

Mike O'Connor - NVIDIA Corporation

Evgeny Bolotin - NVIDIA Corporation

David W. Nellans - NVIDIA Corporation

Justin Luitjens - NVIDIA Corporation

Nikolai Sakharnykh - NVIDIA Corporation

Peng Wang - NVIDIA Corporation

Paulius Micikevicius - NVIDIA Corporation

Anthony Scudiero - NVIDIA Corporation