sponsored byIEEEACMThe International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 16-21, 2014

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Early Evaluation of the SX-ACE Processor

SESSION: Poster Reception


TIME: 5:15PM - 7:00PM

AUTHOR(S):Ryusuke Egawa, Shintaro Momose, Kazuhiko Komatsu, Yoko Isobe, Hiroyuki Takizawa, Akihiro Musa, Hiroaki Kobayashi

ROOM:New Orleans Theater Lobby


Using practical scientific and engineering applications, this poster
presents early performance evaluation of the SX-ACE vector processor, which is the latest vector processor developed by NEC in 2013. While inheriting the advantages of the vector architecture, the SX-ACE processor is designed so as to overcome the drawbacks of conventional vector processors by introducing several architectural features. To unveil the potential of the SX-ACE processor, this poster evaluates and discusses how the brand-new vector processor is beneficial to achieve a high sustained performance on practical science and engineering simulations. Evaluation results show that, for a wide range of practical simulations, SX-ACE potentially achieves a higher sustained performance than its predecessor SX-9 and existing scalar processors.

Chair/Author Details:

Ryusuke Egawa - Tohoku University

Shintaro Momose - NEC Corporation

Kazuhiko Komatsu - Tohoku University

Yoko Isobe - NEC Corporation

Hiroyuki Takizawa - Tohoku University

Akihiro Musa - NEC Corporation

Hiroaki Kobayashi - Tohoku University

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