sponsored byIEEEACMThe International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 16-21, 2014

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BE Session IB: HPC Memory Lane and Future Roadmap (Intro)

SESSION: BE Session IB: HPC Memory Lane and Future Roadmap (Intro)

EVENT TYPE: HPC Interconnections (BE, Undergraduates, Cluster)

TIME: 11:15AM - 12:00PM


Presenter(s):John Shalf



The talk will provide an overview of the challenges posed by the physical limitations of the underlying silicon based CMOS technology, introduce the next generation of emerging machine architectures, and the anticipated effect on the way we program machines in the future.

For the past twenty-five years, a single model of parallel programming (largely bulk-synchronous MPI), has for the most part been sufficient to permit translation of this into reasonable parallel programs for more complex applications. In 2004, however, a confluence of events changed forever the architectural landscape that underpinned our current assumptions about what to optimize for when we design new algorithms and applications. We have been taught to prioritize and conserve things that were valuable 20 years ago, but the new technology trends have inverted the value of our former optimization targets. The time has come to examine the end result of our extrapolated design trends and use them as a guide to re-prioritize what resources to conserve in order to derive performance for future applications. This talk will describe the challenges of programming future computing systems. It will then provide some highlights from the search for durable programming abstractions more closely track track emerging computer technology trends so that when we convert our codes over, they will last through the next decade.

Chair/Presenter Details:

Karla Morris (Chair) - Sandia National Laboratories

John Shalf - Lawrence Berkeley National Laboratory

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