sponsored byIEEEACMThe International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 16-21, 2014

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Using an Adaptive HPC Runtime System to Reconfigure the Cache Hierarchy

SESSION: Memory System Energy Efficiency


TIME: 4:00PM - 4:30PM


AUTHOR(S):Ehsan Totoni, Josep Torrellas, Laxmikant V. Kale



A large portion (40% or more) of a processor's power and energy is consumed by the cache hierarchy. We propose a software-controlled adaptive runtime system-based reconfiguration approach for common HPC applications to save cache energy. Our approach overcomes the two major limitations associated with other methods that turn off ways of set-associative caches: predicting the application's future, and finding the best cache hierarchy configuration. Our approach uses Formal Language Theory to recognize the application's pattern and predict its future. Furthermore, it uses the prevalent Single Program Multiple Data (SPMD) model of HPC codes to find the best configuration in parallel quickly. Our experiments using cycle-accurate simulations indicate that 67% of cache energy can be saved by paying just 2.4% performance penalty on average. Moreover, we demonstrate that for some applications, switching to a software-controlled reconfigurable streaming strategy can improve performance by up to 30% and save 75% of cache energy.

Chair/Author Details:

Alex Ramirez (Chair) - Polytechnic University of Catalonia

Ehsan Totoni - University of Illinois at Urbana-Champaign

Josep Torrellas - University of Illinois at Urbana-Champaign

Laxmikant V. Kale - University of Illinois at Urbana-Champaign

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