sponsored byIEEEACMThe International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 16-21, 2014

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Dissecting On-node Memory Access Performance: A Semantic Approach

SESSION: Performance Measurement


TIME: 11:30AM - 12:00PM

SESSION CHAIR: Shirley Moore

AUTHOR(S):Alfredo Gimenez, Todd Gamblin, Barry Rountree, Abhinav Bhatele, Ilir Jusufi, Peer-Timo Bremer, Bernd Hamann



Optimizing memory access is critical for performance and power efficiency. CPU manufacturers have developed sampling-based performance measurement units (PMUs) that report precise costs of memory accesses at specific addresses. However, this data is too low-level to be meaningfully interpreted and contains an excessive amount of irrelevant or uninteresting information.

We have developed a method to gather fine-grained memory access performance data for specific data objects and regions of code with low overhead and attribute semantic information to the sampled memory accesses. This information provides the context necessary to more effectively interpret the data. We have developed a tool that performs this sampling and attribution and used the tool to discover and diagnose performance problems in real-world applications. Our techniques provide useful insight into the memory behavior of applications and allow programmers to understand the performance ramifications of key design decisions: domain decomposition, multi-threading, and data motion within distributed memory systems.

Chair/Author Details:

Shirley Moore (Chair) - University of Texas at El Paso

Alfredo Gimenez - University of California, Davis

Todd Gamblin - Lawrence Livermore National Laboratory

Barry Rountree - Lawrence Livermore National Laboratory

Abhinav Bhatele - Lawrence Livermore National Laboratory

Ilir Jusufi - University of California, Davis

Peer-Timo Bremer - Lawrence Livermore National Laboratory

Bernd Hamann - University of California, Davis

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Paper also available from IEEE Computer Society