sponsored byIEEEACMThe International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 16-21, 2014

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Managing DRAM Latency Divergence in Irregular GPGPU Applications

SESSION: Memory and Microarchitecture


TIME: 11:30AM - 12:00PM

SESSION CHAIR: Suzanne Rivoire

AUTHOR(S):Niladrish Chatterjee, Mike O'Connor, Gabriel H. Loh, Nuwan Jayasena, Rajeev Balasubramonian



Memory controllers in modern GPUs aggressively reorder
requests for high bandwidth usage, often interleaving requests from
different warps. This leads to high variance in the latency of
different requests issued by the threads of a warp.
Since a warp in a SIMT architecture can proceed only when all of its
memory requests are returned by memory, such latency divergence causes
significant slowdown when running irregular GPGPU applications.

To solve this issue, we propose memory scheduling mechanisms that
avoid inter-warp interference in the DRAM system to reduce the average
memory stall latency experienced by warps. We further reduce latency
divergence through mechanisms that coordinate
scheduling decisions across multiple independent memory channels. Finally we show that carefully
orchestrating the memory scheduling policy can achieve low average
latency for warps, without compromising bandwidth utilization. Our
combined scheme yields a 10.1% performance improvement for irregular
GPGPU workloads relative to a throughput-optimized GPU memory

Chair/Author Details:

Suzanne Rivoire (Chair) - Sonoma State University

Niladrish Chatterjee - NVIDIA Corporation and University of Utah

Mike O'Connor - NVIDIA Corporation

Gabriel H. Loh - Advanced Micro Devices, Inc.

Nuwan Jayasena - Advanced Micro Devices, Inc.

Rajeev Balasubramonian - University of Utah

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Paper provided by the ACM Digital Library

Paper also available from IEEE Computer Society