sponsored byIEEEACMThe International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 16-21, 2014

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Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy

SESSION: Memory and Microarchitecture


TIME: 11:00AM - 11:30AM

SESSION CHAIR: Suzanne Rivoire

AUTHOR(S):Ralph Nathan, Bryan Anthonio, Shih-Lien L. Lu, Helia Naeimi, Daniel J. Sorin, Xiaobai Sun



In this work, we provide energy-efficient architectural support for floating point accuracy. For each floating point addition performed, we “recycle” that operation’s rounding error. We make this error architecturally visible such that it can be used, whenever desired, by software. We also design a compiler pass that allows software to automatically use this feature. Experimental results on physical hardware show that software that exploits architecturally recycled error bits can (a) achieve accuracy comparable to a 64-bit FPU with performance and energy that are comparable to a 32-bit FPU, and (b) achieve accuracy comparable to an all-software scheme for 128-bit accuracy with far better performance and energy usage.

Chair/Author Details:

Suzanne Rivoire (Chair) - Sonoma State University

Ralph Nathan - Duke University

Bryan Anthonio - Cornell University

Shih-Lien L. Lu - Intel Corporation

Helia Naeimi - Intel Corporation

Daniel J. Sorin - Duke University

Xiaobai Sun - Duke University

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Paper also available from IEEE Computer Society