sponsored byIEEEACMThe International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 16-21, 2014

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Runtime Aware Architectures

SESSION: Invited Talks 5

EVENT TYPE: Invited Speakers

TIME: 11:15AM - 12:00PM

SESSION CHAIR: Padma Raghavan

Presenter(s):Mateo Valero

ROOM:New Orleans Theater

ABSTRACT:

In the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore's Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while hardware designers were able to aggressively exploit instruction-level parallelism (ILP) in superscalar processors. Current multi-cores are designed as simple symmetric multiprocessors (SMP) on a chip. However, we believe that this is not enough to overcome all the problems that multi-cores face. The runtime has to drive the design of future multi-cores to overcome the restrictions in terms of power, memory, programmability and resilience that multi-cores have. In this talk, we introduce a first approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime's perspective.

Chair/Presenter Details:

Padma Raghavan (Chair) - Pennsylvania State University

Mateo Valero - Barcelona Supercomputing Center

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