sponsored byIEEEACMThe International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 16-21, 2014

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Failure Avoidance Techniques for HPC Systems Based on Failure Prediction

SESSION: Doctoral Showcase - Dissertation Research II

EVENT TYPE: Doctoral Showcase

TIME: 1:30PM - 1:45PM

SESSION CHAIR: Karen L. Karavanic

Presenter(s):Ana Gainaru

ROOM:386-87

ABSTRACT:

As the size of HPC systems continues to increase, so does the probability of single component failures within a time frame. With MTBFs of less than one day to a few hours for future systems, current fault tolerance strategies face serious limitations. My research focuses on offering ways of reducing the overhead induced by these strategies, by combining them with failure avoidance methods. My key observation that errors are often predicted by changes in the frequency or regularity of various events has encouraged the use of signal analysis concepts for failure analysis. The results on various systems show that signal processing techniques can create clear markers for changes in events behavior. Moreover, machine learning techniques become much more efficient when applied to the derived markers, rather than the original signal. Hybrid fault tolerance strategies based on this novel predictor applied on various systems have shown overhead reductions of over 20%.

Chair/Presenter Details:

Karen L. Karavanic (Chair) - Portland State University

Ana Gainaru - University of Illinois at Urbana-Champaign

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