sponsored byIEEEACMThe International Conference for High Performance 
Computing, Networking, Storage and Analysis
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SCHEDULE: NOV 16-21, 2014

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Evaluation infrastructure for Future Large-Scale Chips and HPC systems

SESSION: Evaluation infrastructure for Future Large-Scale Chips and HPC systems

EVENT TYPE: Birds of a Feather

TIME: 5:30PM - 7:00PM

SESSION LEADER(S):George Michelogiannakis, Farzad Fatollahi-Fard, Dave Donofrio

ROOM:391-92

ABSTRACT:

Future HPC nodes will likely contain processors with thousands of cores and will spark a revolution in virtually all areas of computing. Understanding the complex tradeoffs of this radical shift in computer architecture and its impact on applications will require advanced, multi-resolution simulation and emulation infrastructures. This BoF will focus on the challenges and fundamental tradeoffs in evaluating future many-core chips and exascale systems. The goal is to spark a lively discussion and exchange of opinions and experiences with 5-minute conversation starter presentations on a range of topics including simulation accuracy, fidelity and feasibility.

Session Leader Details:

George Michelogiannakis (Primary Session Leader) - Lawrence Berkeley National Laboratory

Farzad Fatollahi-Fard (Secondary Session Leader) - Lawrence Berkeley National Laboratory

Dave Donofrio (Secondary Session Leader) - Lawrence Berkeley National Laboratory

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