BEGIN:VCALENDAR
PRODID:-//Microsoft Corporation//Outlook MIMEDIR//EN
VERSION:1.0
BEGIN:VEVENT
DTSTART:20141118T173000Z
DTEND:20141118T180000Z
LOCATION:391-92
DESCRIPTION;ENCODING=QUOTED-PRINTABLE:ABSTRACT: Memory controllers in modern GPUs aggressively reorder=0Arequests for high bandwidth usage, often interleaving requests from=0Adifferent warps. This leads to high variance in the latency of=0Adifferent requests issued by the threads of a warp.=0ASince a warp in a SIMT architecture can proceed only when all of its=0Amemory requests are returned by memory, such latency divergence causes=0Asignificant slowdown when running irregular GPGPU applications.=0A=0ATo solve this issue, we propose memory scheduling mechanisms that=0Aavoid inter-warp interference in the DRAM system to reduce the average=0Amemory stall latency experienced by warps. We further reduce latency=0Adivergence through mechanisms that coordinate=0Ascheduling decisions across multiple independent memory channels. Finally we show that  carefully=0Aorchestrating the memory scheduling policy can achieve low average=0Alatency for warps, without compromising bandwidth utilization. Our=0Acombined scheme yields a 10.1% performance improvement for irregular=0AGPGPU workloads relative to a throughput-optimized GPU memory=0Acontroller.
SUMMARY:Managing DRAM Latency Divergence in Irregular GPGPU Applications
PRIORITY:3
END:VEVENT
END:VCALENDAR